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DCT-II algorithm optimised for low power computation
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Hugo Mårdbrink 97973c31e0 Add multicore support for hardware configuration
2024-03-30 22:49:45 +01:00
.gitignore Add naive implementation 2024-03-25 12:14:16 +01:00
CMakeLists.txt Add naive implementation 2024-03-25 12:14:16 +01:00
Design_and_analysis.md Add multicore support for hardware configuration 2024-03-30 22:49:45 +01:00
main.c Add naive implementation 2024-03-25 12:14:16 +01:00
README.md Refer specific information to design document 2024-03-30 19:42:38 +01:00
riscv_hw.py Add multicore support for hardware configuration 2024-03-30 22:49:45 +01:00
toolchain.cmake Add naive implementation 2024-03-25 12:14:16 +01:00

README.md

DCT-II algorithm tailored for RISC-V satellites 🛰️

The goal of this project is to explore a hardware-software co-design approach to the DCT-II algorithm on a RISC-V processor. There is currently a rise of RISC-V processors in the industry, especially in the space domain. I thought it would be interesting to explore the DCT-II algorithm due to its applications in satellites, and its potential to be accelerated. Therefore, this project places emphasis on energy efficient configurations in contrast to maximizing throughput.

For more information refer to the design document.