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Add multicore support for hardware configuration

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Hugo Mårdbrink 2024-03-30 22:49:45 +01:00
parent c2d3c37eb6
commit 97973c31e0
2 changed files with 47 additions and 33 deletions
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58
riscv_hw.py
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@ -1,16 +1,17 @@
import m5
from m5.objects import System, SrcClockDomain, VoltageDomain, Root
from m5.objects import RiscvO3CPU, Cache, AddrRange, SEWorkload, Process
from m5.objects import MemCtrl, DDR3_1600_8x8, SystemXBar, L2XBar, RiscvISA
from m5.objects import System, SrcClockDomain, VoltageDomain, Root, \
RiscvO3CPU, Cache, AddrRange, SEWorkload, Process, MemCtrl, \
DDR3_1600_8x8, SystemXBar, L2XBar, RiscvISA
class RiscvHWConfig:
def __init__(self, l1i, l1d, l2, vlen, elen):
def __init__(self, l1i, l1d, l2, vlen, elen, cores):
self.l1i = l1i
self.l1d = l1d
self.l2 = l2
self.vlen = vlen
self.elen = elen
self.cores = cores
def get_config():
@ -21,8 +22,10 @@ def get_config():
parser.add_argument('--l2', type=str, default='256kB')
parser.add_argument('--vlen', type=int, default=256)
parser.add_argument('--elen', type=int, default=64)
parser.add_argument('--cores', type=int, default=1)
args = parser.parse_args()
return RiscvHWConfig(args.l1i, args.l1d, args.l2, args.vlen, args.elen)
return RiscvHWConfig(args.l1i, args.l1d, args.l2,
args.vlen, args.elen, args.cores)
class L1Cache(Cache):
@ -92,6 +95,24 @@ class L2Cache(Cache):
self.mem_side = bus.cpu_side_ports
def createCPU(l2bus, config):
cpu = RiscvO3CPU()
cpu.isa = RiscvISA(enable_rvv=True, vlen=config.vlen, elen=config.elen)
cpu.icache = L1ICache(config)
cpu.dcache = L1DCache(config)
cpu.icache.connectCPU(cpu)
cpu.dcache.connectCPU(cpu)
cpu.icache.connectBus(l2bus)
cpu.dcache.connectBus(l2bus)
cpu.createInterruptController()
return cpu
config = get_config()
print(f"l1i size: {config.l1i}")
@ -99,6 +120,7 @@ print(f"l1d size: {config.l1d}")
print(f"l2 size: {config.l2}")
print(f"vlen size: {config.vlen} bits")
print(f"elen size: {config.elen} bits")
print(f"cores: {config.cores}")
print("\n")
assert config.vlen >= 2 * config.elen, \
@ -121,35 +143,16 @@ system.clk_domain.voltage_domain = VoltageDomain()
system.mem_mode = 'timing'
system.mem_ranges = [AddrRange('512MB')]
system.cpu = RiscvO3CPU()
system.cpu.isa = RiscvISA(enable_rvv=True, vlen=config.vlen, elen=config.elen)
# Create the L1 caches
system.cpu.icache = L1ICache(config)
system.cpu.dcache = L1DCache(config)
# Connect the caches to the CPU
system.cpu.icache.connectCPU(system.cpu)
system.cpu.dcache.connectCPU(system.cpu)
# Connect the CPU to the L2 bus
system.l2bus = L2XBar()
# Connect the L1 caches to the L2 bus
system.cpu.icache.connectBus(system.l2bus)
system.cpu.dcache.connectBus(system.l2bus)
system.cpu = [createCPU(system.l2bus, config) for _ in range(config.cores)]
# Connect the L2 cache to the CPU side bus
system.l2cache = L2Cache(config)
system.l2cache.connectCPUSideBus(system.l2bus)
# Connect the L2 cache to the memory bus
system.membus = SystemXBar()
system.l2cache.connectMemSideBus(system.membus)
# Connect the CPU to the memory bus
system.cpu.createInterruptController()
system.mem_ctrl = MemCtrl()
system.mem_ctrl.dram = DDR3_1600_8x8()
system.mem_ctrl.dram.range = system.mem_ranges[0]
@ -161,8 +164,9 @@ system.workload = SEWorkload.init_compatible(binary)
process = Process()
process.cmd = [binary]
system.cpu.workload = process
system.cpu.createThreads()
for cpu in system.cpu:
cpu.workload = process
cpu.createThreads()
# Run SE mode
root = Root(full_system=False, system=system)