Add multicore support for hardware configuration
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2 changed files with 47 additions and 33 deletions
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@ -14,7 +14,7 @@ Thus, the algorithm is used in spacecraft to decrease the amount of image data t
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Since the environment in space is limited, the design needs to focus on an energy efficient design using a small hardware area.
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This alters the focus of the codesign to prefer energy efficiency over throughput or execution time.
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However, the aspect of fast execution times is still highly relevant and a good balance between the two needs to be explored.
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Notably, in current RISC-V space processors there are no vector processing units, making this a interesting aspect.
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## Method
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### Development and evaluation
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@ -24,6 +24,7 @@ For parallelisation, the (OpenMP library)[https://www.openmp.org/] will be used.
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To test and evaluate the software implementation, it will run in the gem5 simulator. The hardware configuration is also done in configuration files for gem5.
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The mock data for the images will be generated in C with nonsensical values. This does not matter since different values will not affect the run time.
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When measuring the performance the sequential time of generating mock data and freeing the memory will be deducted for a true performance reflection.
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For the parts where problem size will increase, performance will be measured by cycles per DCT block.
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### Building
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@ -38,7 +39,7 @@ The following flags will be used based on what functionality is needed:
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- `-lm` for math library
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- `-libomp` for OpenMP library
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- `-O[level]` for different optimisation levels
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- `-march=rv64imafcv` for the RISC-V ISA
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- `-march=rv64imadcv` for the RISC-V ISA
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- `-mabi=lp64d` for the RISC-V ABI
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### Simulating
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@ -51,15 +52,27 @@ The python script for this project is tailored for this project specifically, th
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- `--l2` for the L2 cache size
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- `--vlen` for the vector length
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- `--elen` for the element length
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- `--cores` for the number of cores
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To run the simulation and output the result, the following command is used:
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```bash
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../gem5/build/RISCV/gem5.opt -d stats/ ./riscv_hw.py --l1i 16kB --l1d 64kB --l2 256kB --vlen 256 --elen 64
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../gem5/build/RISCV/gem5.opt -d stats/ ./riscv_hw.py --l1i 16kB --l1d 64kB --l2 256kB --vlen 256 --elen 64 --cores 1
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```
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## Implementation
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### Initial hardware configuration
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For the initial and naive software implementation, some hardware configurations are set. These are:
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- L1 instruction cache size: 16kB
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- L1 data cache size: 64kB
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- L2 cache size: 256kB
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- Vector length: 256
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- Element length: 64
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- Number of threads: 1
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- L1 cache associativity: 2
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- L2 cache associativity: 8
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### Constants and definitions
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Throughout the code, several constants and definitions are defined for ease to try different configurations. These are defined in the following way:
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- `DCT_SIZE` is the size of the DCT block
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@ -75,9 +88,6 @@ This will be done by allocating DCT-blocks heap memory and filling them with dat
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It's important to actually generate all the data and not reuse the same matrices to get realistic cache hits and misses.
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The memory allocation is done in the following way:
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### Initial hardware configuration
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```c
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element_t ***mock_matrices = (element_t ***) malloc(TOTAL_DCT_BLOCKS * sizeof(element_t**));
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for (int i = 0; i < TOTAL_DCT_BLOCKS; i++) {
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58
riscv_hw.py
58
riscv_hw.py
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@ -1,16 +1,17 @@
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import m5
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from m5.objects import System, SrcClockDomain, VoltageDomain, Root
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from m5.objects import RiscvO3CPU, Cache, AddrRange, SEWorkload, Process
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from m5.objects import MemCtrl, DDR3_1600_8x8, SystemXBar, L2XBar, RiscvISA
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from m5.objects import System, SrcClockDomain, VoltageDomain, Root, \
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RiscvO3CPU, Cache, AddrRange, SEWorkload, Process, MemCtrl, \
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DDR3_1600_8x8, SystemXBar, L2XBar, RiscvISA
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class RiscvHWConfig:
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def __init__(self, l1i, l1d, l2, vlen, elen):
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def __init__(self, l1i, l1d, l2, vlen, elen, cores):
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self.l1i = l1i
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self.l1d = l1d
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self.l2 = l2
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self.vlen = vlen
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self.elen = elen
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self.cores = cores
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def get_config():
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@ -21,8 +22,10 @@ def get_config():
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parser.add_argument('--l2', type=str, default='256kB')
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parser.add_argument('--vlen', type=int, default=256)
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parser.add_argument('--elen', type=int, default=64)
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parser.add_argument('--cores', type=int, default=1)
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args = parser.parse_args()
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return RiscvHWConfig(args.l1i, args.l1d, args.l2, args.vlen, args.elen)
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return RiscvHWConfig(args.l1i, args.l1d, args.l2,
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args.vlen, args.elen, args.cores)
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class L1Cache(Cache):
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@ -92,6 +95,24 @@ class L2Cache(Cache):
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self.mem_side = bus.cpu_side_ports
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def createCPU(l2bus, config):
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cpu = RiscvO3CPU()
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cpu.isa = RiscvISA(enable_rvv=True, vlen=config.vlen, elen=config.elen)
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cpu.icache = L1ICache(config)
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cpu.dcache = L1DCache(config)
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cpu.icache.connectCPU(cpu)
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cpu.dcache.connectCPU(cpu)
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cpu.icache.connectBus(l2bus)
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cpu.dcache.connectBus(l2bus)
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cpu.createInterruptController()
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return cpu
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config = get_config()
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print(f"l1i size: {config.l1i}")
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@ -99,6 +120,7 @@ print(f"l1d size: {config.l1d}")
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print(f"l2 size: {config.l2}")
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print(f"vlen size: {config.vlen} bits")
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print(f"elen size: {config.elen} bits")
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print(f"cores: {config.cores}")
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print("\n")
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assert config.vlen >= 2 * config.elen, \
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@ -121,35 +143,16 @@ system.clk_domain.voltage_domain = VoltageDomain()
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system.mem_mode = 'timing'
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system.mem_ranges = [AddrRange('512MB')]
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system.cpu = RiscvO3CPU()
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system.cpu.isa = RiscvISA(enable_rvv=True, vlen=config.vlen, elen=config.elen)
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# Create the L1 caches
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system.cpu.icache = L1ICache(config)
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system.cpu.dcache = L1DCache(config)
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# Connect the caches to the CPU
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system.cpu.icache.connectCPU(system.cpu)
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system.cpu.dcache.connectCPU(system.cpu)
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# Connect the CPU to the L2 bus
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system.l2bus = L2XBar()
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# Connect the L1 caches to the L2 bus
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system.cpu.icache.connectBus(system.l2bus)
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system.cpu.dcache.connectBus(system.l2bus)
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system.cpu = [createCPU(system.l2bus, config) for _ in range(config.cores)]
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# Connect the L2 cache to the CPU side bus
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system.l2cache = L2Cache(config)
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system.l2cache.connectCPUSideBus(system.l2bus)
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# Connect the L2 cache to the memory bus
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system.membus = SystemXBar()
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system.l2cache.connectMemSideBus(system.membus)
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# Connect the CPU to the memory bus
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system.cpu.createInterruptController()
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system.mem_ctrl = MemCtrl()
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system.mem_ctrl.dram = DDR3_1600_8x8()
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system.mem_ctrl.dram.range = system.mem_ranges[0]
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@ -161,8 +164,9 @@ system.workload = SEWorkload.init_compatible(binary)
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process = Process()
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process.cmd = [binary]
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system.cpu.workload = process
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system.cpu.createThreads()
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for cpu in system.cpu:
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cpu.workload = process
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cpu.createThreads()
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# Run SE mode
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root = Root(full_system=False, system=system)
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